1. Field of the Invention
The present invention generally relates to a sensing circuit for multi-level flash memory, and more particularly to a sensing circuit for multi-level flash memory by using voltage division to provide reference voltages.
2. Description of the Prior Art
In conventional memory devices, data is stored in a flash memory cell in the form of electrical charge accumulated inside an inner gate, which is known as a floating gate. The amount of charge stored in the floating gate depends on the voltage applied to the external gate of the memory cell that controls the magnitude of electrical current flowing through it. The data state “0”, or “1”represented by the memory cell depends on whether threshold voltage generated by the stored charge exceeds a specified threshold voltage or not. However, such conventional memory has the limitation that one memory cell can distinguish only two different states, i.e., one memory cell can store only one-bit of data. As a result, limited storage capacity becomes a disadvantage of conventional memory device.
FIG. 1 illustrates an improved multi-level flash memory sensing circuit according to known arts. In the circuit, a flash memory cell capable of storing two bits of data was shown. A flash memory constructed from such kind of cells can thus provide double storage capacity within the same dimension. FIG. 1 contains a reference voltage generator, a data saving circuit, a comparing circuit and a decoder 145. The reference voltage generator, which includes resistive devices 100, 103, 106, bit line clamp circuits 112, 115, 118, and the reference memory cells 124, 127, 130, is to provide different reference voltage levels REF1, REF2, and REF3.
The data saving circuit, which includes a resistive device 109, a bit line clamp circuit 121, and a flash memory cell 133, is for storing digital information. The comparing circuit, which includes comparators 136, 139, and 142, is intended to compare the voltage level stored in the data saving circuit with the voltage level generated by the reference voltage generator. The comparing circuit sends digital signals representing the comparing result to the decoder 145, and the decoder 145 decodes information stored in the flash memory cell 133 according to the permutation of the digital signals.
A key factor that the circuit shown in FIG. 1 can store two bits of digital data is that it contains a reference voltage generator which is designed to output several different reference voltage levels. In the example of FIG. 1, three different reference voltage levels will be generated to distinguish four distinct voltage ranges. By the comparing circuit, it can determine to which range the voltage level is stored in the data saving circuit, then it is able to decode the information stored in the data saving circuit.
FIG. 2 shows aforementioned three reference voltage levels REF1, REF2, REF3 as well as four voltage ranges defined thereby. Specifically, we have a first range with a voltage level less than REF1, a second range with a voltage level between REF1 and REF2, a third range with a voltage level between REF2 and REF3, and a fourth range with a voltage level greater than REF3. Vh1 represents the voltage level kept in the data saving circuit. The flash memory cell is said to keep information “A” when Vh1 is in the first range. Likewise, the flash memory cell is said to respectively keep information “B”, “C”, or “D” when Vh1 is in the second, third, or fourth range. States “A” through “D” can be represented by two bits of digital code in this case. “00”, for example, can be assigned to state “A”, “01” can be assigned to “B”, “10” can be assigned to “C”, and “11” can be assigned to “D”. Alternatively, “11,10,01,00” or any other different permutation can be assigned to states “A,B,C,D” respectively.
As the reference voltage generator provides more different voltage levels, and thus more voltage ranges, more information represented by the flash memory cell of the data saving circuit, will be able to be discriminated. A disadvantage of the circuit shown in FIG. 1 is, however, that the same number of reference voltage generating units must be provided to generate the required number of reference voltage levels. Each reference voltage generating unit includes one resistive device, one bit line clamp circuit, and one reference memory cell. On the other hand, before each reference voltage generating unit is qualified to work, they must be calibrated for the correct voltage level output, and the calibration process needs some duration of testing time. Moreover, except the range under the smallest reference voltage level and the range above the largest reference voltage level (such as the first and the fourth ranges in FIG. 2), all the other ranges (such as the second and the third ranges in FIG. 2) must meet a requirement that their extent should be constant, i.e., the difference between any two adjacent reference voltage levels has to be fixed.
In view of the impact of the number of reference voltages on both the data storage capacity and the testing duration for reference voltage calibration process, and the requirement of constant reference voltage ranges, there is a need to provide an improved reference voltage generator for the sensing circuit for multi-level flash memory to resolve above problems.